http://www.dynalith.com/ 2012-05-18T23:24:49+09:00 http://www.dynalith.com/ http://www.dynalith.com/lib/images/favicon.ico text/html 2007-06-04T16:51:19+09:00 http://www.dynalith.com/doku.php?id=amba&rev=1180943479 iPROVE AMBA design kit provides an ideal FPGA-based virtual prototype environment for rapid creation of AMBA-based IP and Soc design and verification. This toolkit is designed to provide both hardware and software designers with easy-to-use development environment, in which designers just specify AMBA bus configuration and pick design blocks and connect them to the AMBA bus to build a complete AMBA system. With the generated AMBA system, designers can run their application program on the host co… text/html 2009-11-17T15:31:43+09:00 http://www.dynalith.com/doku.php?id=app_note&rev=1258439503 * Application Note for iNEXT * Application Note for iNTUITION * Application Note for iNCITE * Application Note for OpenJTAG * Application Note for OpenIDEA * Application Note for iPROVE * Application Note for iTUTOR * Application Note for iSAVE text/html 2007-06-05T15:14:49+09:00 http://www.dynalith.com/doku.php?id=award&rev=1181024089 Dynalith is a member of USB Implementers Forum, Inc. that is a non-profit corporation founded by the group of companies that developed the Universal Serial Bus specification. (www.usb.org) Dynalith Systems is providing a high-quality design service based on FPGA and its products as a member of Xilinx Alliance Program. <http://www.xilinx.com> Dynalith’s logic simulation acceleration technology has been approved as a Korean New Excellent Technology by the Ministry of Science and Technology… text/html 2009-11-17T13:20:27+09:00 http://www.dynalith.com/doku.php?id=brochure&rev=1258431627 * Dynalith Systems’ Technologies and Products [PDF] * iNEXT Brochure [PDF] * iNTUITION Brochure [PDF] * iNCITE-5000 Brochure [PDF] * iNCITE Brochure [PDF] * iNCITE-APP Brochure [PDF] * OpenJTAG Brochure [PDF] * OpenRISC System Development Package [PDF] * OpenIDEA Brochure [PDF] * iNSPIRE Brochure [PDF] * Remote Emulation Brochure [PDF] * iCON Brochure [PDF] * GLKB Brochure [PDF] * All-in-One Audio/Video Capture and Test Brochure [PDF] * iTUTOR Brochur… text/html 2007-06-05T16:29:25+09:00 http://www.dynalith.com/doku.php?id=career&rev=1181028565 If you are interested in the following jobs, please contact at <job-opp@dynalith.com>. Senior Field Applications Engineer (Korea) * Job description: * Pre-sales demonstrations and post-sales support our customers. * Qualifications: * Three or more years of experience * Must be able to design using Verilog and/or VHDL * Must have experience with industry standard HDL logic simulators and logic synthesizers * Must have experience with FPGA, especially Xilinx * Hav… text/html 2011-03-17T09:46:09+09:00 http://www.dynalith.com/doku.php?id=contact_address&rev=1300322769 Headquarters: Dynalith Systems Co., Ltd. * 8 Gangnam-daero 34, (14-2 Yangjae-Dong), Taejin B/D, 3F, Seocho-Gu, Seoul 137-888, Korea * 서울시 서초구 강남대로 34길 8번지 (양재동 14-2) 태진빌딩 3층 (137-888) * Tel: +82-2-556-0020 * Fax: +82-2-556-2252 * E-mail: <contact@dynalith.com> text/html 2009-11-17T13:37:45+09:00 http://www.dynalith.com/doku.php?id=copyright_trademarks&rev=1258432665 Dynalith Systems Web Server Copyright Copyright ⓒ 2002-2009 Dynalith Systems Co., Ltd. All rights reserved. Unless otherwise noted, any person is hereby authorized to view, copy, and print these documents subject to the following conditions: * This document may be used for informational purposes only. * Any copy of this document or portion thereof must include the copyright notice. * This information is provided “AS IS” and without warranty of any kind, express, implied, statut… text/html 2011-07-07T14:42:29+09:00 http://www.dynalith.com/doku.php?id=core-a&rev=1310017349 Core-A embedded processor RTL source * Core-A 1st Generation ISA * 32-bit RISC and 5-stage pipeline implementation * Original version: Free of charge, but agreement required * Dynalith proprietary version: Feature added version, license required * On-Chip Debugger, Tightly-Coupled Memory, AHB supporting, AXI supporting text/html 2007-06-05T14:50:38+09:00 http://www.dynalith.com/doku.php?id=executive_summary&rev=1181022638 iSAVE (in-System Algorithm Verification Engine) is the industry’s first & unique toolkit for the early functional verification of the behavioral model of the target ASIC, or complex FPGA (Field Programmable Gate Array) described in C, C++ or its dialects. With iSAVE, algorithm to be implemented as an ASIC or complex FPGA (more than several million gates with or without processor core embedded) can be verified in the context of real target board before the RTL/Gate level design is available. Th… text/html 2007-07-26T11:14:40+09:00 http://www.dynalith.com/doku.php?id=ignite&rev=1185416080 iPROVE iGnite is an HDL front-end interface meaning that users can import Verilog-HDL instead of EDIF at the beginning of project. iGnite is a GUI-based design flow navigator with features of handing Verilog, automatic generation of synthesis and P&R scripts. iGnite also provides signal probing feature in which users can use the same signal name as RTL code. In addition to this, unlimited depth and width of monitoring is possible at a cycle-level co-emulation mode. text/html 2008-09-26T10:30:16+09:00 http://www.dynalith.com/doku.php?id=incite-avrem&rev=1222392616 The iNCITE-AVREM is an application board for iNCITE baseboard and provides various peripherals. * Audio Codec * 1Headphone jack * Microphone jack * Microphone (optional) * Video DAC * RS-343A 15-pin D-Sub female connector * RS-232C line-driver * RS-232C 9-pin D-Sub female connector text/html 2008-09-26T10:38:03+09:00 http://www.dynalith.com/doku.php?id=incite-wapp&rev=1222393083 The [INCITE-WAPP] is an application board for iNCITE baseboard and provides various wireless peripherals. * IrDA * Communication distance: 20cm ~ 100cm * Interface: Serial transmitting receiving line * Bluetooth module * Bluetooth specification v1.2 * Communication distance: up to 30m * Frequency range: 2.4GHz ISM Band * Transmit power: 2dBm(Typical) * Support Bluetooth Profile: SPP * Communication Speed: 1,200bps ~ 115,200bps * Interface: UART(TTL level) text/html 2008-09-26T10:51:23+09:00 http://www.dynalith.com/doku.php?id=incite&rev=1222393883 What is iNCITE iNCITE is an FPGA board that connects to the host computer through high-speed USB. iNCITE is targeted for the development of small and medium digital logic with various memories and peripherals as a general purpose FPGA development platform. There are three versions of iNCITE according to FPGA size, which are iNCITE-5000, iNCITE-2000 and iNCITE-1000. text/html 2010-01-08T10:09:07+09:00 http://www.dynalith.com/doku.php?id=incite_examples&rev=1262912947 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iNCITE related products, but WITHOUT ANY WARRANTY. iNCITE-5000 No. Title Doc. Down 11 iNCITE Quick Tutorial - Transaction Level - revised for iNSPIRE-2.0 [ZIP] 10 iNCITE Quick Tutorial - Cycle Level Using C - revised for iNSPIRE-2.0 [ZIP] 09 iNCITE Quick Tutorial - Cycle Level Using Verilog - revised for iNSPIRE-2.0 [ZIP] 08 Verification of Edge Detect Design us… text/html 2007-06-06T14:58:32+09:00 http://www.dynalith.com/doku.php?id=incite_japan&rev=1181109512 text/html 2011-03-24T10:52:39+09:00 http://www.dynalith.com/doku.php?id=inext-v6&rev=1300931559 iNEXT-V6 is the upgraded version of iNEXT. The key differences are * Capacity increased: Xilinx V6-760, up to 4 FPGAs * Enable to use DDR3: Supports DDR3, DDR2 and EXD-MEM (SSRAM and Flash) * Host Interface performance enhanced - PCI Express ’ text/html 2009-04-09T11:14:25+09:00 http://www.dynalith.com/doku.php?id=inext&rev=1239243265 iNEXT is a multi-FPGA board with host interface through PCI-Express and USB 2.0 to provide hardware engineers with modeling and debugging toolkit in addition to accelerating functionality, it has C/C++ API, Verilog PLI/VPI, and VHDL VHPI for easy-to-use test-bench development. The iNEXT supports PC Windows and Linux, up to four Xilinx Virtex-5 LX330, and various memories including DDR2, SDRAM, SRAM, and Flash.’’ text/html 2010-02-18T10:21:26+09:00 http://www.dynalith.com/doku.php?id=inext_examples&rev=1266456086 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iNEXT related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down 11 Simple OpenRISC embedded SoC on iNEXT [PDF] [ZIP] 10 How To Generate DDR2 Controller for iNEXT using Xilinx MIG [PDF] 09 Multi-FPGA Co-Emulation using iNEXT: SRAM controller [PDF] [ZIP] 08 SystemC Co-Emulation using iNEXT: 32×32 Multiplier Case [PDF] [ZIP] 07 Verification of TEA using i… text/html 2008-10-01T13:47:23+09:00 http://www.dynalith.com/doku.php?id=inspire&rev=1222836443 iNSPIRE is an integrated design environment for FPGA-based emulation platforms. With iNSPIRE, you can build SoC emulation environment for a series of Dynalith’s verification products very easily. Designers just import their own design and select target emulation hardware, then iNSPIRE will generate all stuffs required to start emulation. text/html 2007-07-26T15:01:34+09:00 http://www.dynalith.com/doku.php?id=inspire_download&rev=1185429694 No Title Download 4 SystemC library for iNTUITION 3 iNSPIRE for iNTUITION V1.0 build 36 2 iNSPIRE for iNTUITION V1.0 build 26 1 iNSPIRE for iNTUITION V1.0 build 10 DOWN text/html 2011-06-09T09:58:42+09:00 http://www.dynalith.com/doku.php?id=inspire_examples&rev=1307581122 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iNSPIRE related products, but WITHOUT ANY WARRANTY. Tools Tool Description Version Support Platform Down eifgen generation of EIF from TCF 2.13 iNCITE, iNTUITION, iNEXT Windows Linux rbt2tcf generation of TCF from RBT 2.16 iNCITE, iNTUITION, iNEXT Windows Linux eifman manipulation of filds of EIF 2.9 iNCITE, iNTUITION, iNEXT Windows L… text/html 2007-06-05T14:47:27+09:00 http://www.dynalith.com/doku.php?id=introduction&rev=1181022447 Mission Dynalith Systems develops and markets specialized hardware and CAD solutions that enable electronic system designers to verify their algorithms in real hardware environments at an early design stage and, thereby significantly reduce time-to-market. ’ text/html 2008-09-26T10:47:43+09:00 http://www.dynalith.com/doku.php?id=intuition-muv&rev=1222393663 As an iNTUITION application board, iNTUITION-MUV is connected through the board-to-board connector, i.e. Z-Pack connector and provides various memories and peripherals. * SDRAM components * 2 SDRAM components * 32-bit data bus * 8Mbyte capacitance for each, i.e., 16Mbyte total * Two 8Mbyte with 32-bit data width by default text/html 2009-11-17T13:49:56+09:00 http://www.dynalith.com/doku.php?id=intuition&rev=1258433396 iNTUITION is a general purpose prototyping system with high-density FPGA-based simulation acceleration capability and easy-to-use built-in logic analyzer, which fits the best with the requirements targets the physical prototyping platform for processing-core-embedded systems such as SoC and embedded-system.’ text/html 2011-06-08T16:03:22+09:00 http://www.dynalith.com/doku.php?id=intuition_examples&rev=1307516602 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iNTUITION related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down 6 Co-emulation of a DCT/IDCT in iNTUITION [PDF] [ZIP] 5 Co-emulation of a 2D-IDCT in iNTUITION [PDF] [ZIP] 4 Reference Design for iNTUITION [PDF] [ZIP] 3 Co-emulation of a Multiplier in iNTUITION [PDF] [ZIP] 2 SRAM test example using BFM in iNTUITION board [PDF] [ZIP] 1 LED test examp… text/html 2007-06-04T16:11:03+09:00 http://www.dynalith.com/doku.php?id=iprove&rev=1180941063 Dynalith Systems’ iPROVE (Intelligent PROtotype Verification Engine) offers the solution for such problems in SoC design and verification. iPROVE can verify the user’s design by mapping the HDL description of each design onto an FPGA card. Prior to be fabricated in Silicon, once software simulation with HDLs is completed, iPROVE downloads the design into FPGAs and does design verification. In software simulation, after the completion of verification in RTL, the design should be synthesized … text/html 2007-07-26T11:38:08+09:00 http://www.dynalith.com/doku.php?id=iprove_examples&rev=1185417488 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iPROVE related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down text/html 2007-06-06T15:09:02+09:00 http://www.dynalith.com/doku.php?id=isave-mp&rev=1181110142 Overview Dynalith Systems’ SoC Design platform, iSAVE-MP, provides a seamless design platform for HW/SW co-design and co-verification for SYSTEM-on-a-Chip (SoC). Designers can verify their ASIC or SoC design from the architecture level to the register-transafer level (RTL) using iSAVE-MP, which supports multiple languages (C/C++, SystemC, HDL, and EDIF)and mixed levels (behavioral to cycle-level).’ text/html 2007-06-06T15:10:19+09:00 http://www.dynalith.com/doku.php?id=isave-p3x2&rev=1181110219 Fast in-system verification of C-based design with up to 50MHz signal speed depending on circuit complexity * Supports up to 240 IO signal pins * Automated translation of C model for porting into iSAVE (IOnization) through GUI * Automated generation of user IO model * Built-in signal analyzer (PSA: 96 pins, 33MHz sampling, 64Kcycles) * Supports direct plug-in and cable extension to target chip socket * Supports various package types * Interface protocol libraries provided … text/html 2007-07-27T12:34:47+09:00 http://www.dynalith.com/doku.php?id=isave_examples&rev=1185507287 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iSAVE related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down text/html 2007-07-26T11:20:15+09:00 http://www.dynalith.com/doku.php?id=itutor&rev=1185416415 It is highly required that digital logic designers have to be trained from conceptual design to FPGA-based prototyping. To support this requirement, Dynalith developed cost-effective version of PCI card, which is iTUTOR and contains Xilinx Spartan 3. text/html 2007-07-26T14:37:13+09:00 http://www.dynalith.com/doku.php?id=itutor_examples&rev=1185428233 Notice : The contents in this example page are prepared in the hope that it will be useful to understand iTUTOR related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down 11 32×32 Multiplier Case with iTUTOR [PDF] [ZIP] 10 iTUTOR SystemC Co-Emulation: TEA Example [PDF] [ZIP] 09 iTUTOR Introduction and Quick Tutorial [PDF] [ZIP] 08 iTUTOR on-board SSRAM interfacing example [PDF] [ZIP] 07 UART Testing Example Using iTUTOR and GLKB [PDF] [ZIP] 06 UART test e… text/html 2007-07-26T16:42:16+09:00 http://www.dynalith.com/doku.php?id=management_team&rev=1185435736 Jong-Suk Kim / President & CEO * ECAD development, System IC development and sales, marketing in Hyundai Electronics Industries, Co., Ltd. * MSME KAIST * BSME Seoul National University Chong-Min Kyung, Ph.D / CTO * Director, IC Design Education Center (IDEC) (present) * Director, Center for High-Performance Integrated Systems (present) * Department Chairman, Dept. of Electrical Engineering, KAIST * Professor of Electrical Engineering, KAIST (present) * Bell Telephone La… text/html 2009-11-17T13:35:43+09:00 http://www.dynalith.com/doku.php?id=manual&rev=1258432543 Manuals listed below are available at Download section of Product for registered customers. (SUPPORT) iNEXT manuals * iNEXT Executive Summary * iNEXT PCI Express Installation Guide * iNEXT User Manual * iNEXT-VIO User Manual * iNSPIRE for iNEXT - User Guide text/html 2007-06-05T15:36:45+09:00 http://www.dynalith.com/doku.php?id=map&rev=1181025405 Headquarters in Seoul Korea How to get to KAIST R&D Center in KAIST text/html 2007-06-06T15:11:37+09:00 http://www.dynalith.com/doku.php?id=multi-isave&rev=1181110297 Fast in-system verification of C-based design with up to 50MHz signal speed depending on circuit complexity * Supports up to 240 IO signal pins * Automated translation of C model for porting into iSAVE (IOnization) through GUI * Automated generation of user IO model * Built-in signal analyzer (PSA: 96 pins, 33MHz sampling, 64Kcycles) * Supports direct plug-in and cable extension to target chip socket * Supports various package types * Interface protocol libraries provided * Ea… text/html 2010-07-07T17:52:28+09:00 http://www.dynalith.com/doku.php?id=openidea&rev=1278492748 OpenIDEA is an integrated SoC development environment based on open source hardware and software. OpenIDEA along with iNSPIRE and iNCITE offers all design and verification tools for OpenRISC-based embedded SoC, including software development, hardware generation, ISS(Instruction-Set-Simulator)-based software simulation, S/W-H/W co-simulation and FPGA-based prototyping board. text/html 2009-09-22T15:49:04+09:00 http://www.dynalith.com/doku.php?id=openidea_examples&rev=1253602144 Notice : The contents in this example page are prepared in the hope that it will be useful to understand OpenIDEA related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down 13 DMA Controller Example: Opencores Wishbone dma Case [PDF] on request 12 Audio Play Example [PDF] [ZIP] 11 VGA Example [PDF] [ZIP] 10 uIP-based Webserver using OpenRISC-embedded SoC [PDF] on request 9 Building a Simple Platform using OpenRISC and Wishbone [PDF] on request 8 Building … text/html 2008-09-26T10:38:29+09:00 http://www.dynalith.com/doku.php?id=openjtag&rev=1222393109 OpenJTAG is a USB-driven JTAG interface. For brochures, please refer to this page. For software download, please refer to this page. For example programs, please refer to this page. OpenJTAG as an in-circuit debugger hardware, supports Beyond BA12 processor, OpenRISC and its compatible cores. OpenJTAG works with OpenIDEA, which is OpenRISC software development studio. text/html 2008-09-29T14:40:15+09:00 http://www.dynalith.com/doku.php?id=openjtag_examples&rev=1222666815 Notice : The contents in this example page are prepared in the hope that it will be useful to understand OpenIDEA related products, but WITHOUT ANY WARRANTY. No. Title Doc. Down 2 How To Use OpenJTAG with OpenIDEA [PDF] on request 1 JTAG Scan [Down] text/html 2007-06-07T20:41:25+09:00 http://www.dynalith.com/doku.php?id=papers_articles&rev=1181216485 * System-on-a-Chip design and verification (Part6),, Ando Ki, IDEC Newsletter, Vol. 116, pp.16-18, Feb. 2007. (Korean) * System-on-a-Chip design and verification (Part5), Ando Ki, IDEC Newsletter, Vol. 115, pp.14-19, Jan. 2007. (Korean) * SoC project through IDEC MPW (II), M.K. Chung, IDEC Newsletter, Vol. 115, pp.8-12, Jan. 2007. (Korean) * System-on-a-Chip design and verification (Part4), Ando Ki, IDEC Newsletter, Vol. 114, pp.16-19, Dec. 2006. (Korean) * SoC project through I… text/html 2008-06-08T13:38:11+09:00 http://www.dynalith.com/doku.php?id=partners&rev=1212899891 Impulse Accelerated Technologies, Inc <http://www.impulseC.com> Impulse products allow developers of advanced embedded, DSP and image processing systems to rapidly move applications originating in ANSI C to FPGA coprocessors. The Impulse CoDeveloper tools are in use by software and hardware application developers worldwide. For more information on Impulse C-to-FPGA, visit www.ImpulseC.com.’’’ text/html 2007-06-05T12:14:26+09:00 http://www.dynalith.com/doku.php?id=press_kit&rev=1181013266 Corporation Logo logo.gif logo_trans.gif logo_inverse.gif Products iprove_x2.gif text/html 2011-01-07T09:59:40+09:00 http://www.dynalith.com/doku.php?id=press_release&rev=1294361980 English * “Xilinx‐based Hardware/Software Co‐simulation Accelerated on Dynalith/Impulse C to FPGA Prototyping System”, , Jan 2010. [PDF] * PCI-Express External Cabling Solution using Xilinx Virtex-5 LXT FPGA by Dynalith Systems”, Dynalith Systems, June 2007. [PDF] * “Dynalith’ announced 10 Million gate version iPROVE”, Dynalith Systems, March 10th, 2005. [PDF] * “Dynalith’s iPROVE supports SCE-MI”, DAC-2004 at San Diego, CA. June 7th, 2004. [PDF] * “Dynal… text/html 2007-06-05T11:46:59+09:00 http://www.dynalith.com/doku.php?id=press_room&rev=1181011619 This page contains on-line catalog and technical documents published on journals and conferences. To see the materials in the Papers & Articles page, your name and e-mail address will be asked. The information gethered in the page will be used by Dynalith Systems to support you as our potential customer. text/html 2011-09-08T15:06:24+09:00 http://www.dynalith.com/doku.php?id=product_chinese&rev=1315461984 * iNEXT * Brochure : [PDF] text/html 2008-10-28T14:00:15+09:00 http://www.dynalith.com/doku.php?id=product_japanese&rev=1225170015 <http://www.spinnaker.co.jp/EDA/Dynalith.html> * iNEXT * Brochure : [PDF] * Executive Summary: [PDF] * Brochure of iPROVE : [PDF] * Brochure of iNCITE :[PDF] * Brochure of iCON-USB : [PDF] text/html 2010-05-11T17:19:35+09:00 http://www.dynalith.com/doku.php?id=products&rev=1273565975 iNEXT FPGA-based logic simulator and virtual prototyping system * Multi-FPGA (Xilinx Virtex-5 LX 33Million x 4) * PCI express based host-interface channel * Software-FPGA co-running * HDL simulator-FPGA co-simulation * Built-in logic analyzer * Various memories supported: DDR2/SDRAM/SSRAM/Flash * Up to 314 external IO supported text/html 2007-09-13T10:28:53+09:00 http://www.dynalith.com/doku.php?id=qanda&rev=1189646933 Please contact <support@dynalith.com> text/html 2008-09-25T16:49:43+09:00 http://www.dynalith.com/doku.php?id=sce-mi&rev=1222328983 iPROVE SCE-MI co-emulation co-modeling provides an environment in which C-level (i.e., UTC and RTC) models cooperate with the post-synthesis blocks in the hardware accelerator (i.e., iPROVE) through the SCE-MI infrastructure. As the picture shows, user’s DUT and its transactor are mapped on the FPGA in the iPROVE and the testbench written in C++ or SystemC runs on the host computer where the SCE-MI infrastructure is prepared by the iPROVE SCE-MI software. text/html 2009-11-17T15:22:31+09:00 http://www.dynalith.com/doku.php?id=site_map&rev=1258438951 Home * Home * What's New * Events Products * iNEXT * iNEXT * iNTUITION * iNTUITION * iNCITE * iNCITE * iNCITE-AVREM * iNCITE-WAPP * iNSPIRE * iNSPIRE * AMBA * AMBA * OpenJTAG * OpenJTAG * OpenIDEA * OpenIDEA text/html 2008-06-12T10:30:47+09:00 http://www.dynalith.com/doku.php?id=ssuccessstory_openvg&rev=1213234247 Abstract System Design Group in Seoul National University (sdgroup.snu.ac.kr, led by Prof. Soo-Ik Chae) verified OpenVG 2D Vector Graphics Engine using iNTUITION prototyping board which is suitable development kit for video and graphics system including SDRAM, TFT-LCD, etc. Most computational blocks in graphics engine are implemented by dedicated hardware and off-chip SDR SDRAM memory is used. The system is developed on SoCBase platform provided by Center for SoC Design Technology in Seoul Nati… text/html 2010-05-06T16:15:19+09:00 http://www.dynalith.com/doku.php?id=ssuccessstory_raytrace&rev=1273130119 Abstract A Whitted-style Ray tracing accelerator is implemented. It achieves about 2.6M rays per second over realistic 3D scenes. The Ray Tracing core operates 48 MHz on iNEXT with 2-FPGAs. [PDF] [Demo Video] <http://rayman.sejong.ac.kr> text/html 2009-10-16T14:45:17+09:00 http://www.dynalith.com/doku.php?id=ssuccessstory_snu_flora&rev=1255671917 Abstract FloRA is a coarse-grained reconfigurable array architecture with floating-point operation capability. FloRA is implemented as a chip in Dongbu HiTek 130nm process, and is evaluated using iNEXT board. We demonstrate JPEG decoder and fractal tree generation at DAC’09 university booth. [PDF] [Demo Video] text/html 2007-07-20T12:25:26+09:00 http://www.dynalith.com/doku.php?id=start&rev=1184901926 text/html 2007-06-06T15:44:12+09:00 http://www.dynalith.com/doku.php?id=success_intuition_h264_etri&rev=1181112252 Abstract A H.264 decoder system is implemented using iNTUITION in which ARM11, LCD, FPGA and various memories are used. The H.264 decoder core is implemented as an AMBA AHB slave IP so that it can be easily integrated with the AMBA-based SoC. The decoder is designed to cooperate with special SDRAM controller utilizing SDRAM page mode to maximize the memory bandwidth at the lowest memory operation speed for low-power application. [PDF] text/html 2010-05-06T16:18:20+09:00 http://www.dynalith.com/doku.php?id=success_stories&rev=1273130300 No. Title Abstract Full Text Demo Video 27 Verification of H.264 High/Baseline Profile Codec using iNEXT Multi-FPGA System ABSTRACT [PDF] 26 An Implementation of iNCITE-FVT through JTAG ABSTRACT [PDF] 25 Evaluation and Demonstration of FloRA Chip using iNEXT ABSTRACT [PDF] [Down(5.75MB)] 24 An Implementation of full Whitted-style Ray Trace with iNEXT ABSTRACT [PDF] [Down(44.9MB)] 23 Verification of OpenVG 2D Vector Graphics Engine with SoCBase Platform using iNTUITION ABS… text/html 2007-07-26T17:44:40+09:00 http://www.dynalith.com/doku.php?id=successstory_aes&rev=1185439480 Abstract A full design-flow from algorithmic level in the C language down to FPGA-based emulation through behavioral and RT level has been established, where AES is used as an example design. In order to recover speed down as abstraction level is getting lower, hardware-based co-emulation technique is adopted, where iPROVE provides 70 times faster result compared to software simulation of RTL version. [PDF] text/html 2007-07-26T17:44:01+09:00 http://www.dynalith.com/doku.php?id=successstory_audiodsp_ajou&rev=1185439441 Abstract iPROVE gives many benefits in the course of DSP verification, such like a faster simulation and FPGA-based gate-level verification. iPROVE also provides an easy way to migrate from HDL simulation to FPGA-based co-simulation/emulation by sharing the same test-bench. [PDF] text/html 2007-08-01T11:52:33+09:00 http://www.dynalith.com/doku.php?id=successstory_convergensc_kaist&rev=1185936753 Abstract iPROVE, FPGA-based hardware accelerator from Dynalith Systems, has been integrated with ConvergenSC, SystemC based simulator from CoWare, to provide a means of running ESL design along with hardware in the FPGA. [PDF] text/html 2007-07-26T17:45:32+09:00 http://www.dynalith.com/doku.php?id=successstory_eisc_adc&rev=1185439532 Abstract Speedup of x1000 times has been achieved with iPROVE compared to pure software simulation, where all components of ADC EISC AE32000-based SoC are mapped into the FPGA on the iPROVE and its execution results are displayed on the external graphical LCD display. [PDF] text/html 2007-07-26T17:45:17+09:00 http://www.dynalith.com/doku.php?id=successstory_ieee802.11a_cbu&rev=1185439517 Abstract Acceleration of 116~35463 times has been delivered for IEEE 802.11a design, where codec & modem parts are running on the iPROVE and application & MAC parts are running on the host computer. [PDF] text/html 2007-07-26T17:45:44+09:00 http://www.dynalith.com/doku.php?id=successstory_ieee802.11a_icu&rev=1185439544 Abstract iPROVE simulates WLAN IEEE 802.11a design 2.8 times faster than RTL simulation using pure software simulator. This result is very noticeable, since Celaro and System Explorer only accelerate 1.1 and 1.7 times. [PDF] text/html 2008-06-12T10:27:40+09:00 http://www.dynalith.com/doku.php?id=successstory_impulsec&rev=1213234060 Abstract HW and SW produced from C program through Impulse CoDevelopment environment are applied to Dynalith iNCITE, where HW part is put into FPGA while SW part is run in the PC Windows. For the integration of Impulse C and Dynalith iNCITE, hardware library and software API library are developed. [PDF] text/html 2009-11-05T10:50:57+09:00 http://www.dynalith.com/doku.php?id=successstory_incite_fvt_kor&rev=1257385857 Abstract JTAG을 통해 SOC 내부의 FVT(주파수, 전압, 온도)를 모니터링 할 수 있는 시스템이 성공적으로 수행되었다. 온도, 전압, 주파수 정보가 포함된 시스템은 iNCITE와 FVT 보드로 구성되었으며, JTAG 신호를 통해 FVT(주파수, 전압, 온도)를 읽어오는 기능은 OpenJTAG 이 담당한다. text/html 2007-07-26T17:42:52+09:00 http://www.dynalith.com/doku.php?id=successstory_incite_uwb_keri_v4&rev=1185439372 Abstract KERI (Korea Electrotechnology Research Institute) succeeded demonstration of impulse radio- based Ultra-Wideband (IR-UWB) wireless communication system by taking full advantage of FPGA and fast USB connection of iNCITE. A PC having music files transfers the audio data stream through USB and then UWB wireless channel to another PC that plays the received music, where ‘Dynalith Systems’ iNCITE is used to connect the PC and UWB block. [PDF] text/html 2010-02-22T16:57:05+09:00 http://www.dynalith.com/doku.php?id=successstory_inext_h.264_etri_v1.4&rev=1266825425 Abstract H.264 high and baseline profile codec systems are implemented on Virtex-5 multi-FPGA board. The codec supports full HD class video and the FPGA board called iNEXT consists of up to four 33-million FPGA [PDF] text/html 2007-10-29T13:29:11+09:00 http://www.dynalith.com/doku.php?id=successstory_intuition_h.264_cosoc_v1&rev=1193632151 Abstract Center for SoC Design Technology (CoSoC) at Seoul National University developed H.264 decoder, which is implemented on iNTUITION that has Virtex-4 (XC4VLX200) and ARM926EJ-S CoreTile. The H.264 decoder runs at 37MHz and decodes 30fps of QVGA. [PDF] text/html 2007-07-26T17:43:19+09:00 http://www.dynalith.com/doku.php?id=successstory_intuition_h264_kaist&rev=1185439399 Abstract Inverse transform and deblocking filter of Advanced Video Coding Standard H.264 decoder are implemented. The decoder design uses 4×4 sub-block pipeline for a higher performance and performs 30 frames per second for CIF movie clips with 25Mhz on the iNTUITION. [PDF] text/html 2007-07-26T17:42:19+09:00 http://www.dynalith.com/doku.php?id=successstory_intuition_mission-3d_samsungait_v2&rev=1185439339 Abstract Rasterizer for Mobile 3D graphics engine is successfully verified and demonstrated on iNTUITION platform. Rasterizer module is integrated into ARM11-based SoC design which is implemented on two Xilinx Virtex-4 LX200 FPGAs of iNTUITION and extension boards. Microsoft Windows CE .NET 5.0 operating system is running on this hardware platform in order to verify 3D graphics accelerator design in a real environment. [PDF] text/html 2007-10-29T13:28:35+09:00 http://www.dynalith.com/doku.php?id=successstory_intuition_vc1_cosoc_v1&rev=1193632115 Abstract System Design Group in Seoul National University (sdgroup.snu.ac.kr, led by Prof. Soo-Ik Chae) verified a VC-1 decoder using iNTUITION prototyping board which is suitable development kit for video decoding system including SDRAM, TFTLCD, etc. Most computational blocks in decoding system are implemented by dedicated hardware and we exploited two types of off-chip memories, SDR SDRAM and DDR2 SDRAM. The system is developed on SoCBase platform provided by Center for SoC Design Technology … text/html 2007-07-26T17:43:07+09:00 http://www.dynalith.com/doku.php?id=successstory_intuition_windows_ce&rev=1185439387 Abstract Board Support Package (BSP) for Microsoft Windows CE .NET 5.0 for iNTUITION is implemented. iNTUITION is the hardware and software co-development environment where customer’s ARM-based SoC design and Windows-CE based embedded software are running together and eventually possible errors of both sides are fixed at the early design stage. [PDF] text/html 2007-07-26T17:43:33+09:00 http://www.dynalith.com/doku.php?id=successstory_maxsim_kaist&rev=1185439413 Abstract iPROVE, FPGA-based hardware accelerator from Dynalith Systems, has been incorporated with MaxSim, SystemC based simulator from ARM, to provide a complete functional verification flow, in which SystemC, legacy HDL, and post-synthesis design are supported. [PDF] text/html 2007-07-26T17:44:14+09:00 http://www.dynalith.com/doku.php?id=successstory_mjpeg_hynix&rev=1185439454 Abstract M-JPEG (Motion JPEG) encoder has been verified at gate-level, where image sensor board is connected to the M-JPEG encoder mapped on iPROVE through DPP and the encoded image is displayed at the host computer. This configuration demonstrates real-time encoding of 640×480 color image at 15 frames per second. [PDF] text/html 2007-07-26T17:43:46+09:00 http://www.dynalith.com/doku.php?id=successstory_mpeg4_samsung&rev=1185439426 Abstract An MPEG4 codec based on hierarchical AMBA bus has been verified using FPGAembedded PCI boards on the Linux PC system. The design is partitioned and mapped on two FPGA-embedded PCI boards and its input and output including camera and display are modeled on the host computer. This configuration works 8.6K times faster than pure software simulation. In addition to the speedup, this approach removes physicalprototyping step completely. [PDF] text/html 2007-07-26T17:45:06+09:00 http://www.dynalith.com/doku.php?id=successstory_multiiprove&rev=1185439506 Abstract A JPEG decoder composed of ARM processor and IDCT IP is emulated using two iPROVE cards. Bus splitter circuit is utilized to span on-chip AHB bus over multiple FPGAs. It synchronizes AHB bus signals in several FPGAs in time-multiplexed fashion using 33MHz synchronization clock. Overall system is emulated in 6.6MHz operating frequency. [PDF] text/html 2007-07-26T17:44:27+09:00 http://www.dynalith.com/doku.php?id=successstory_probase_kaist&rev=1185439467 Abstract ProBase platform consisting of FPGA and ARM core module has been developed, which combines ICE-based software debugging and iPROVE-based hardware debugging features. [PDF] text/html 2007-07-26T17:44:54+09:00 http://www.dynalith.com/doku.php?id=successstory_rcm_snu&rev=1185439494 Abstract As coarse-grained reconfigurable architectures have become more attractive with the increas-ing demand of more flexibility and higher performance in embedded systems design, a synthe-sizable coarse-grained reconfigurable architecture is implemented and confirmed its behavioral correctness using iPROVE which gives 7 ~ 9 times faster result than pure software simulator. [PDF] text/html 2007-07-26T17:45:55+09:00 http://www.dynalith.com/doku.php?id=successstory_reconfigurable_etri&rev=1185439555 Abstract A reconfigurable processor has been verified at gate-level using iPROVE and MPEG4 application without making FPGA prototype board. [PDF] text/html 2007-08-24T11:24:19+09:00 http://www.dynalith.com/doku.php?id=successstory_scp_koreau&rev=1187922259 Abstract Security Camera Processor (SCP) is implemented and demonstrated with iNCITE. iNCITE is FPGA board which can support USB connection in order to execute HW-SW co-emulation. So, SCP function could be easily demonstrated using iNCITE’s feature. SCP is designed to realize portable security camera system. SCP always observes the image of target place, using CIS. When the motion is detected, SCP starts to store still image of target place with JPEG encoding. After storing, user can decode… text/html 2007-07-26T11:15:00+09:00 http://www.dynalith.com/doku.php?id=systemc&rev=1185416100 iPROVE SystemC Co-Emulation package provides an easy-to-use design flow for co-running post-synthesis hardware blocks with SystemC simulator. With this co-emulation environment, designers can verify SystemC based designs along with hardware IP and can refine SystemC models from functional level to gate-level through RT-level.