| No. | Title | Abstract | Full Text | Demo Video |
| 27 | Verification of H.264 High/Baseline Profile Codec using iNEXT Multi-FPGA System | ABSTRACT | PDF | |
| 26 | An Implementation of iNCITE-FVT through JTAG | ABSTRACT | PDF | |
| 25 | Evaluation and Demonstration of FloRA Chip using iNEXT | ABSTRACT | PDF | Down(5.75MB) |
| 24 | An Implementation of full Whitted-style Ray Trace with iNEXT | ABSTRACT | PDF | Down(44.9MB) |
| 23 | Verification of OpenVG 2D Vector Graphics Engine with SoCBase Platform using iNTUITION | ABSTRACT | PDF | |
| 22 | Dynalith Demonstrates Host Program Driven FPGA Co-Simulation using Impulse C | ABSTRACT | PDF | |
| 21 | Verification of VC-1 decoder with SoCBase Platform using iNTUITION | ABSTRACT | PDF | |
| 20 | Verifying H.264 Decoder System using iNTUITION | ABSTRACT | PDF | |
| 19 | Implementation of Security Camera Processor with iNCITE | ABSTRACT | PDF | |
| 18 | Integration of CoWare ConvergenSC and Dynalith iPROVE | ABSTRACT | PDF | |
| 17 | Rapid Prototyping of H.264 Decoder using iNTUITION | ABSTRACT | PDF | |
| 16 | 3D Graphics Hardware Accelerator with iNTUITION | ABSTRACT | PDF | |
| 15 | Impulse Radio-Based Ultra-Wideband (IR-UWB) Demonstration Using iNCITE | ABSTRACT | PDF | |
| 14 | Microsoft Windows CE 5.00 Porting on iNTUITION | ABSTRACT | PDF | |
| 13 | Verification of H.264 Decoder with iPROVE and iNTUITION | ABSTRACT | PDF | |
| 12 | iPROVE has been connected with ARM MaxSim Design Flow - Center for SoC Design Technology | ABSTRACT | PDF | |
| 11 | Verification of MPEG4 Codec with Virtual Platform Environment | ABSTRACT | PDF | |
| 10 | DSP Core Simulation Acceleration using iPROVE | ABSTRACT | PDF | |
| 09 | Real-Time Demonstration Environment of M-JPEG using iPROVE | ABSTRACT | PDF | |
| 08 | ARM and FPGA based Co-Emulator for SoC Design and Verification - ProBase from Center for SoC Design Technology - | ABSTRACT | PDF | |
| 07 | Co-Emulation of Pipelined AES using iPROVE within SystemC Environment | ABSTRACT | PDF | |
| 06 | Verification of Coarse-Grained Reconfigurable Architecture Using iPROVE | ABSTRACT | PDF | |
| 05 | Transaction-Level Verification of JPEG SoC Using Multiple iPROVE | ABSTRACT | PDF | |
| 04 | Verification of IEEE 802.11a Base-Band Processor using iPROVE | ABSTRACT | PDF | |
| 03 | Full Scale SoC Emulation Using iPROVE -ADC EISC AE32000 Case - | ABSTRACT | PDF | |
| 02 | Logic Simulation Acceleration of IEEE 802.11a WLAN | ABSTRACT | PDF | |
| 01 | Functional Verification of Reconfigurable Processor using Co-Running Feature of FPGA and C program | ABSTRACT | PDF | |
