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Papers & Articles

  1. Functional verification of IP using BFM, Ando Ki, IDEC Newsletter, Vol. 131, pp.4- 9, May 2008. (Korean)
  2. Transacton-level modeling of SoC, Ando Ki, IDEC Newsletter, Vol. 126, pp.9- 11, Dec. 2007. (Korean)
  3. FPGA-Based Simulation for Rapid Prototyping, Ando Ki, Xilinx Xcell Journal Issue 61, Third Quarter 2007.
  4. Functional verification using virtual prototyping,, Ando Ki, IT-SoC Magazine, p.31-36, July 2007. (Korean)
  5. System-on-a-Chip design and verification (Part6),, Ando Ki, IDEC Newsletter, Vol. 116, pp.16-18, Feb. 2007. (Korean)
  6. System-on-a-Chip design and verification (Part5), Ando Ki, IDEC Newsletter, Vol. 115, pp.14-19, Jan. 2007. (Korean)
  7. SoC project through IDEC MPW (II), M.K. Chung, IDEC Newsletter, Vol. 115, pp.8-12, Jan. 2007. (Korean)
  8. System-on-a-Chip design and verification (Part4), Ando Ki, IDEC Newsletter, Vol. 114, pp.16-19, Dec. 2006. (Korean)
  9. SoC project through IDEC MPW (I), M.K. Chung, IDEC Newsletter, Vol. 114, pp.12-15, Dec. 2006. (Korean)
  10. System-on-a-Chip design and verification (Part 3), Ando Ki, IDEC Newsletter, Vol. 113, pp.16-19, Nov. 2006. (Korean)
  11. System-on-a-Chip design and verification (Part 2), Ando Ki, IDEC Newsletter, Vol. 112, pp.14-18, Oct. 2006. (Korean)
  12. System-on-a-Chip design and verification (Part I), Ando Ki, IDEC Newsletter, Vol. 111, pp.16-18, Sept. 2006. (Korean)
  13. Advent of SystemVerilog as an HDVL language, Ando Ki, SIPAC Newsletter, Vol.5, No.5, pp.12-13, Sept-Oct., 2005. (Korean)
  14. Hands-on tutorial on HW-SW co-simulation and co-emulation for SoC design and verification, Ando Ki, ISOCC-2005, Oct. 2005
  15. HW-SW Co-Simulation and Co-Emulation for SoC Design and Verification, Ando Ki, ISOCC-2005, Oct. 2005
  16. Reducing Lock-Step Overhead of Hardware-Assisted Simulation Acceleration using Protocol Awareness, Ando Ki and Young-Il Kim, ISOCC-2005, Oct. 2005.
  17. Simultaneous Hardware and Software Simulation, Ando Ki, IDEC Newsletter, Dec. 2004, pp.10-13. (Korean)
  18. Efficient DSP Core Architecture for High-quality Audio Algorithms, Jong H. Moon, Myung H. Sunwoo, International SoC Design Conference, Oct. 2004, pp.17-20.
  19. Implementation of Efficient Transactor for iPROVE Chong-hyun Cho, Chan-jong Woo, Joong-hwee Cho, International SoC Design Conference, Oct. 2004, pp.404-407.
  20. Optimistic Channel Usage between Simulator and Simulation Accelerator, Jae-Gon Lee, Chong-Min Kyung, International SoC Design Conference, Oct. 2004, pp.392-395.
  21. Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator, Young-Su Kwon, Jae-Gon Lee, Chong-Min Kyung, International SoC Design Conference, Oct. 2004, pp.218-301.
  22. SoC Design Environment with Automated Bus Architecture Generation for Rapid Prototyping with ISS, Sang-Heon Lee, Jae-Gon Lee, Ando Ki, Chong-Min Kyung, International SoC Design Conference, Oct. 2004, pp.5-8.
  23. How much speedup can be achieved?, Ando Ki, Technical Memo, Dynalith Systems, July 2004.
  24. Principles of SoC(VI), Il-Gu Lee, Jin Lee, Sin-Jong Park, SITI Newsletter, Jan. 2004.
  25. Hardware Based Simulation Environment for Progressive Refinement Methodology, Bong-Il Park, Chang-Ock Kang, Young-Su Kwon, Ando Ki, SoC Design Conference 2003, COEX ASEM Hall, Seoul Korea, Nov. 5-6, 2003.
  26. Cycle-Accurate Co-Emulation with SystemC, Ando Ki, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung, SoC Design Conference 2003, COEX ASEM Hall, Seoul Korea, Nov. 5-6, 2003.
  27. Learning SystemC (Part 4 of 4), Wooseung Yang, IDEC Newsletter, Vol 77, Nov. 2003, pp.24-29. (Korean)
  28. Learning SystemC (Part 3 of 4), IDEC Newsletter, Vol 76, Oct. 2003, pp.24-27. (Korean)
  29. SystemC and Hardware Co-Emulation, Ando Ki, Embedded World, pp.114-119, Nov. 2003. (Korean)
  30. Virtual Prototyping for SoC Design and Verificatioin, Ando Ki, The Magazine of the IEEK, Vol. 30, No.9, pp.965-975 (59-69), Sept. 2003. (Korean)
  31. Learning SystemC (Part 2 of 4), Ando Ki, IDEC Newsletter, Vol 75, Sept. 2003, pp.22-25. (Korean)
  32. Learning SystemC (Part 1 of 4), Ando Ki, IDEC Newsletter, Vol 74, Aug. 2003, pp.20-25. (Korean)
  33. SoC Emulation in Multiple FPGA using Bus Splitter, Wooseung Yang, IEEK Summer Conference, Vol 26, No.1, Jul. 2003, pp.859-862.
  34. In-Circuit System-on-Chip Verification and Debugging Environment, IEEK Summer Conference, Vol. 26, No.1, Jul. 2003, pp.1007-1010.
  35. AES Design and Verification using iPROVE, SIPAC Korea 2003. (Korean)
  36. An Implementation of Pipelined Rijndael with SystemC and Co-emulation with iPROVE , SNUG(Synopsys Users Group) Korea 2003.
  37. IP-Based Design and SoC Verification, Real-Time Embedded World, English Edition, Spring. 2003, pp.34-39.
  38. IP/SoC Design and Verification using iPROVE and iSAVE, Semiconductor Monthly Korea, No. 178, Dec. 2002, pp.60-67. (Korean)
  39. Block-based SoC design and verification, Test & Measurement - The Magazine for Quality in Electronics , Vol. 7, Sept. 2002, pp.81-85. (Korean)
  40. Refinement procedure of C programs for modeling and implementation using a behavioral emulation system, W.S.Yang et.al., The 9th Korean Conference on Semiconductors, Feb. 2002, pp.105-106. (Korean)
  41. Design trends using the C language -- the C language as a design language for system and non-memory devices, Ando Ki, The Magazine of the IEEK, Vol. 29, No.1, Jan. 2002, pp.93-97. (Korean)
  42. A study of the match-on-card system for the user authentication, S.B.Pan, Y.W.Chung et.al., The 2nd Korean Workshop on Biometrics Technology, 2002.1.17, p.16-20. (A demonstration set was developed using iSAVE-P3X2 and Training Kit) (Korean)
  43. Parallel modeling of MPEG2 decoder and verification using behavioral-level emulation, S.T.Lim et.al. The 14th Workshop on Image Processing and Image Understanding, 2002.1.9-11, p.311-314. (Korean)
  44. In-system verification with the C language, W.S.Yang et.al., IC Design Education Center Newsletter 2001. Volume 59, p.28-31. (Korean)
 

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