iSAVE MP

Dynalith Systems’ SoC Design platform, iSAVE-MP, provides a seamless design platform for HW/SW co-design and co-verification for SYSTEM-on-a-Chip (SoC).

Designers can verify their ASIC or SoC design from the architecture level to the register-transafer level (RTL) using iSAVE-MP, which supports multiple languages (C/C++, SystemC, HDL, and EDIF)and mixed levels (behavioral to cycle-level).

iSAVE-MP’s hardware utilizes multi-processor architecture to provide scalable computing power, multiple Split Target interface ARchitectures(STARs) to provide scalable target interfaces, and Reconfigurable FPGA Engine (RFE) modules to support HDL design. Embedded system design using processor cores, such as ARM and DSP cores, are supported.

iSAVE-MP provides easy-to-use verification environment using Linux-based stand alone system. iSAVE-MP is easily incorporated with existing design blocks described either in HDL or in EDIF. Moreover, iSAVE-MP has various options to extend design and verification environments such as C-based design, in-system verification and embedded core design.

Designer can choose a transaction-based mode for fast verification and a cycle-based mode for signal-level verification using iSAVE-MP.

It also provides various debugging features for an easy development environment. These features include a source level debugger, Pin Signal Analyzer (PSA) and Software Variable Analyzer (SVA).

• Powerful processing engine
  • Linux-based stand-alone solution
  • Scalable computing power with multi-processor architecture
  • Scalable target interfacing capabilities with multiple STARs

• Powerful processing engine
  • C/C++, SystemC, Verilog, VHDL, EDIF
  • HDL design supported directly with RFE modules

• Multiple verification mode
  • Transaction-based mode for fast verification
  • Cycle-level mode for signal level verification

• Powerful debugging capabilities
  • Pin Signal Analyzer (PSA), a built-in logic analyzer with triggering support, enables the user to monitor the pin signals
  • Software Variable Analyzer (SVA) enables tracing software variables
  • GNU DeBugger (GDB)-based debugger for software debugging

• Easy-to-use graphical user interface

• In-system verification

For more information