iPROVE
Dynalith Systems’ iPROVE (Intelligent PROtotype Verification Engine) offers the solution for such problems in SoC design and verification. iPROVE can verify the user’s design by mapping the HDL description of each design onto an FPGA card.
Prior to be fabricated in Silicon, once software simulation with HDLs is completed, iPROVE downloads the design into FPGAs and does design verification. In software simulation, after the completion of verification in RTL, the design should be synthesized for netlist generation. Moreover, verification time of the functionality for the netlist takes tens or hundreds times longer than the one in a RTL level.
However, by using iPROVE, users can map their design into FPGAs and execute design verification with less time. The verification speed with iPROVE reaches tens to hundreds times faster than conventional verification tools. Also, with transaction-level, iPROVE provides even higher performance so that iPROVE supports well the large size designs.
iPROVE combines all the benefits of a FPGA prototyping with many flexible features of software simulation. iPROVE provides many features, such as a higher performance, realistic results and better signal debugging capability. It also gives software’s flexibility by handling various high-level languages as well as HDLs.
iPROVE provides a number of invaluable features, which enable designers to test/verify and debug their design while the application program is running on the host computer and the design is running in FPGAs inside of iPROVE hardware. These features include interfacing, debugging and the external connection.
- Interfacing features
- C/C++ API enables designers to develop their testbench using high-level languages.
- HDL PLI/FLI enables designers to use their HDL simulation environment with a minor modification.
- Generalized interfacing mechanism between SW simulation and HW emulation provides HW-SW co-development, where the former runs in the host computer and the latter runs in the iPROVE hardware.
- Debugging features
- Built-in-logic-Analyzer (BILA) is embedded in iPROVE. Using this feature, users can observe signals in the DUT that is mapped into FPGA of iPROVE.
- External connection features
- A Data Pumping Port (DPP) enables the DUT to send and/or receive data.
Using the features of iPROVE, a wide range of applications is possible as follows.
- Chip design: Blocks/modules to be tested can be easily verified with remaining blocks in various formats, e.g., C/C++/HDL/EDIF and other already verified IP blocks can be simulated.
- IP development: A wider freedom of testbench development is possible and the hardware prototyping can be possible to deliver highly reliable IP’s.
- Device driver development: Hardware prototype is available prior to getting a real chip.
- PCI card development: A pilot hardware prototype board can be easily developed on the PCI interface, i.e, iProveBaseBoard.
- HW/SW co-verification: Software models on the host computer can be co-simulated with hardware prototype in iPROVE.
- General testbench environment: iPROVE API/PLI/FLI provides a wider range of freedom to develop testbench.
- Hardware acceleration: The DUT in the iPROVE hardware is likely to run faster than software simulation.
- In-system verification: The DPP provides a mechanism to connect external devices.
iPROVE’s software package provides a device driver for following Operating Systems.
- Microsoft’s Windows 2000
- Microsoft’s Windows XP
As iPROVE utilizes FPGA, HDL synthesizers and P&R software tools are required. The following HDL synthesizers can be used for iPROVE.
- Synopsys’ Design Compiler with feature of FPGA Compiler
- Synopsys’ FPGA Compiler II
- Mentor Graphics’ Leonardo Spectrum
- Synplicity’s Synplify Pro
- Xilinx’ XST
- Altera’s Quartus II (will be supported shortly)
As iPROVE only imports DUT in EDIF format, other HDL synthesizers will not cause problems. The following P&R software is also required.
- Xilinx’ ISE for Xilinx version of iPROVE
- Altera’s Quartus II for Altera version of iPROVE (will be supported shortly)
While iPROVE accommodates DUT in its hardware, the host computer runs testbench or remaining blocks of user design. An HDL simulator and/or C/C++ compiler are needed depending on the testbench. When the testbench or remaining block is written in HDLs, the following software simulators can be used.
- Model Technology (Mentor Graphics) ModelSim PE/SE/XE/AE
Generally speaking, iPROVE software package includes PLI library for Verilog and FLI library for VHDL so that any HDL simulators can be run with iPROVE.
When the testbench is written in C/C++, the following C/C++ compilers can be used, but not limited to.
- Microsoft Visual Studio 6.0 Visual C++
- Borland C++ Builder 6.0 (will be supported shortly)
- Borland C++ 5.5
- GNU gcc with Cygwin
iPROVE follows an open interfacing paradigm, meaning that iPROVE does not limit users to interface any possible computers and software tools. To support this paradigm, Dynalith Systems will add more compatible tools. From the users’ point of view, iPROVE is based on APIs including PLI and FLI. As a result, users can easily build their own interfaces on top of the APIs. To demonstrate this approach, the following de facto standards are supported or will be supported.
- SCE-API/MI from Accellera Interfaces Technical Committee
- SystemC from Open SystemC Initiative
- TestBuilder from Cadence Design Systems
- OpenVera from Synopsys