Executive Summary

iSAVE (in-System Algorithm Verification Engine) is the industry’s first & unique toolkit for the early functional verification of the behavioral model of the target ASIC, or complex FPGA (Field Programmable Gate Array) described in C, C++ or its dialects. With iSAVE, algorithm to be implemented as an ASIC or complex FPGA (more than several million gates with or without processor core embedded) can be verified in the context of real target board before the RTL/Gate level design is available. This allows one to find functional design bugs and problems earlier, and as a result, to significantly reduce the time-to-market, which is the name of the game in the extremely competitive chip and electronics market.

Immediately after its incorporation, Dynalith Systems has raised first round capital from Korean domestic investors, Mirae Asset Capital, Mirae Asset Venture Investment and Hyundai Investment Trust & Securities Co., Ltd. Dynalith Systems is planning to raise the second round capital funding to deploy its unrivaled technical competitiveness in high level design verification technology to the fast changing and growing VLSI (Very Large Scale Integration) and systems design industry. The major portion of the funds will be devoted to expansion of our R&D and application development teams and the development toward a further enhancement of the function and capacity of iSAVE.